Power semiconductor devices are widely used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the art including, for example, power Metal Oxide Semiconductor Field Effect Transistors (“MOSFET”), Insulated Gate Bipolar Transistors (“IGBT”), Schottky diodes, Junction Barrier Schottky (“JBS”) diodes, merged p-n Schottky (“MPS”) diodes, Gate Turn-Off Transistors (“GTO”), MOS-controlled thyristors and various other devices. Modern power semiconductor devices are generally fabricated from monocrystalline silicon semiconductor material, or, more recently, from silicon carbide (“SiC”). Moreover, power semiconductor devices are often fabricated in a paralleled unit cell structure.
Power semiconductor devices can have a lateral structure or a vertical structure. In a lateral structure, the terminals of the device (e.g., the drain, gate and source terminals for a power MOSFET device) are on the same major surface (i.e., top or bottom) of a semiconductor layer structure. In contrast, in a vertical structure, terminals are provided on both major surfaces of the semiconductor layer structure (e.g., in a vertical MOSFET, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. Herein, the term “semiconductor layer structure” refers to a structure that includes at least two semiconductor layers in a stacked relationship or to at least a single semiconductor layer having regions that are doped with different types of dopants.
A conventional SiC power device typically has a SiC substrate such as a SiC wafer having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer having the first conductivity type (e.g., n-type) is formed. This epitaxial layer (which may comprise one or more separate layers) functions as a drift region of the power semiconductor device. The device typically includes an “active region” which includes one or more power semiconductor devices that have a p-n junction and/or a Schottky junction. The active region may be formed on and/or in the drift region. The active region acts as a main junction for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. As will be discussed below, the device has an edge termination region that is adjacent the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will typically have its own edge termination. After the substrate is fully formed and processed, the substrate may be diced to separate the individual edge-terminated power semiconductor devices. In many cases, the power semiconductor devices on the substrate will have a unit cell structure in which the active region of each power semiconductor device includes a large number of individual devices that are disposed in parallel to each other and that together function as a single power semiconductor device.
As noted above, semiconductor power devices are designed to block (in the reverse blocking state) or pass (in the forward operating state) large voltages and/or currents. For example, in the reverse blocking state, a semiconductor power device may be designed to sustain tens, hundreds or thousands of volts of electric potential, or even higher voltages. However, as the reverse voltage approaches or passes the reverse voltage level that the device is designed to block, non-trivial levels of current may begin to flow through the power semiconductor device. Such current, which is typically referred to as “leakage current,” may be highly undesirable. Leakage current may begin to flow if the reverse voltage is increased beyond the design voltage blocking capability of the device, which is a function of, among other things, the doping and thickness of the drift layer. However, current leakage can occur for other reasons, such as failure of the edge termination and/or the primary junction of the device.
FIG. 1 is a log-linear graph that schematically illustrates the leakage current characteristics for a conventional SiC power JBS Schottky diode. As shown in the graph of FIG. 1, the reverse leakage current (IR) of the JBS diode increases with increasing reverse voltage (VR). The reverse voltage VR at which the reverse leakage current IR reaches a predetermined level I0 is defined as the rated breakdown voltage (VBR) of the device. As the reverse voltage VR on the diode is increased past the breakdown voltage VBR to a critical level which is referred to as the theoretical avalanche breakdown point (VAV), the increasing electric field begins to ionize atoms within the semiconductor device, leading to a condition known as avalanche breakdown. When avalanche breakdown occurs, the reverse current increases sharply and typically becomes uncontrollable. Such failures are generally catastrophic, and may damage or destroy the device.
A conventional power semiconductor device may begin to break down and allow non-trivial amounts of leakage current to flow at a voltage that is lower than the design breakdown voltage VBR of the device. In particular, leakage current may begin to flow at the edges of the active region, where high electric fields may be experienced due to electric field crowding effects. In order to reduce this electric field crowding (and the resulting increased leakage currents), edge termination structures are provided that surround part or all of the active region of a power semiconductor device. These edge terminations may spread the electric field out over a greater area, thereby reducing the electric field crowding. One known type of edge termination is a junction termination extension (“JTE”).
A JTE edge termination typically surrounds the active region of a power semiconductor device, and may include a plurality of “zones” that have a conductivity type that is opposite the conductivity type of the drift region of the device (e.g., a p-type region with respect to the example SiC power device discussed above). The JTE zones are typically formed by ion implantation, although they can also be formed in other ways (e.g., by growing doped layers, by diffusion, etc.). In SiC power devices having p-type JTE zones, the implanted dopants used to form the JTE zones may be aluminum, boron, or any other suitable p-type dopant. The implanted dopants of the opposite conductivity type spread the electrical field in the reverse blocking state over a greater distance (as compared to a device without a JTE edge termination). Consequently, the JTE edge termination may reduce or prevent the electric field crowding at the edges of the active region, and may also reduce or prevent the depletion region from interacting with the surface of the device. Surface effects may cause the depletion region to spread unevenly, which may adversely affect the breakdown voltage of the device. While a JTE edge termination is one known type of edge termination, other edge termination techniques are also known in the art including, for example, guard rings.
A conventional JTE-terminated Schottky power diode 10 is illustrated in FIG. 2. It will be appreciated that FIG. 2 and the various other cross-sectional diagrams included in this application only illustrates one half of the power semiconductor device structure in order to simplify the drawings; the structure may include mirror image portions (not shown). As shown in FIG. 2, the JTE edge terminated Schottky diode 10 includes an n− drift layer 22 on an n+ substrate 24. The substrate 24 may comprise, for example, an n+ SiC wafer. However, any suitable substrate may be used. The substrate 24 may be optional (e.g., it can be removed after device formation). The drift layer 22 may comprise an epitaxially-grown n− SiC drift layer. At least one p+ region 26 is formed, typically by ion implantation, in an upper surface of the n− drift layer 22. These p+ regions 26 form respective p-n junctions with the drift layer 22. A metal anode Schottky contact 29 is on the drift layer 22 and may be in contact with both the n− drift layer 22 and the p+ region(s) 26. The anode contact 29 forms a Schottky junction with the exposed portions of the drift layer 22, and may form an ohmic contact with the p+ region(s) 26. A metal cathode contact 28 is formed on the opposite side of the n+ substrate 24. The p+ regions 26, the Schottky contact 29, the drift layer 22, the substrate 24 and the cathode contact 28 comprise a Schottky diode that is formed in an active region 20.
In forward operation, a junction J1 between the metal anode Schottky contact 29 and the drift layer 22 turns on before the junctions J2 between the p+ regions 26 and the drift layer 22. Thus, at low forward voltages, the device exhibits Schottky diode behavior. That is, current transport in the device is dominated by majority carriers (electrons) injected across the Schottky junction J1 at low forward voltages. Under reverse bias conditions, however, the depletion regions formed by the p-n junctions J2 between the p+ regions 26 and the drift layer 22 expand to block reverse current through the device 10, protecting the Schottky junction J1 and limiting reverse leakage current in the device 10. Thus, in reverse bias, the JBS diode 10 behaves like a PIN diode. The voltage blocking ability of the device 10 is typically determined by the thickness and doping of the drift layer 22 and the design of any edge termination.
Referring again to FIG. 2, the Schottky power diode 10 further includes a JTE edge termination 30 that includes a plurality of JTE zones 32A, 32B, 32C that are provided in the n− drift layer 22 adjacent to the p+ regions 26. The JTE zones 32A, 32B, 32C are p-type regions that may have levels of charge that decrease outwardly in a stepwise fashion with distance from the active region 20. Although three JTE zones 32A, 32B, 32C are illustrated, more or fewer JTE zones 32 may be provided.
The JTE zones 32A, 32B, 32C may be formed by implantation of ions into the n− drift layer 22. However, since the JTE zones 32A, 32B, 32C have different levels of p-type dopants, such implantation may require multiple mask and implantation steps, increasing the complexity and expense of production. This may be exacerbated as the number of JTE zones 32 is increased.